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MAX19700 Evaluation Kit/Evaluation System
MAX19700 Power-Down
The MAX19700 features a global device power-down
pin. Jumper JU2 controls this feature. See Table 1 for
jumper configuration.
Table 1. Power-Down Shunt Settings (JU2)
Rx ADC Inputs
Although the MAX19700 accepts differential analog
input signals, the EV kit only requires a single-ended
analog input signal, with an amplitude of less than
4.5dBm provided by the user. Connect the single-ended
sources to J3 (I channel) and J6 (Q channel). Insertion
SHUNT
POSITION
1-2*
2-3
PD PIN
OVDD
DGND
DESCRIPTION
Normal operation
MAX19700 powered down
losses due to a series-connected filter and the intercon-
necting cables will decrease the amount of power seen
at the EV kit input. Account for these losses when setting
the signal generator amplitude. On-board transformers
(T1-T2) convert the single-ended analog input signals
* Default configuration: JU2 (1-2).
Measuring the OVDD Supply Current
The level-translating buffer (U2) requires a voltage sup-
ply on each side of the device. By default, the
MAX19700 side of the device is connected to OVDD. If
the OVDD current is measured at the OVDD and GND
pads of the EV kit, a measurement error will occur due
to the extra current flowing into U2. To accurately mea-
sure OVDD current, connect the MAX19700 side of U2
to BVCC by configuring jumper JU5. See Table 2 for
jumper configuration. Ensure that BVCC is equal to
OVDD, when operating in this mode.
Table 2. OVDD Supply Connections (JU5)
and generate differential analog signals at the ADCs ’
differential input pins. The MAX19700 also accepts sin-
gle-ended input signals. See the Configuring for Single-
Ended ADC Operation section in this document for
details on how to modify the MAX19700 EV kit to sup-
port this mode of operation.
Configuring for Single-Ended ADC Operation
The MAX19700 can be configured to accept AC-cou-
pled single-ended signals presented at the input.
Configure the EV kit to support this mode of operation
by completing the steps below:
1) Cut the trace at locations R11, R12, R13, and R14.
2) Install 0 ? resistors at locations R7, R8, R9, R10,
R15, and R16.
SHUNT POSITION
1-2*
2-3
DESCRIPTION
Normal operation
OVDD measurement mode;
note BVCC must equal OVDD
3) Install 2k ? ±1% resistors at locations R21, R22,
R23, and R24.
4) Connect the single-ended sources to J2 (I channel)
and J5 (Q channel).
* Default configuration: JU5 (1-2).
Clock
An on-board clock-shaping circuit generates a clock
signal from an AC sine-wave signal applied to the
CLOCK SMA connector. The input signal should not
exceed a magnitude of 2.6V P-P . The frequency of the
signal should not exceed 7.5MHz for the MAX19700.
The frequency of the sinusoidal input signal determines
the sampling frequency (f CLK ) of the MAX19700. A dif-
ferential line receiver (U3) processes the input signal to
generate the CMOS clock signal. The signal ’ s duty
cycle can be adjusted with potentiometer R63. A clock
signal with a 50% duty cycle (recommended) can be
achieved by adjusting R63 until 1.32V is produced
across test points TP3 and TP4 when the clock voltage
supply (CVDD) is set to 3.0V. The clock signal is avail-
able at J11-1 (CLK), which can be used to synchronize
the output signal to the logic analyzer. Measure the
clock signal with an oscilloscope at TP5.
Configure the EV kit for DC-coupled single-ended sig-
nals by removing capacitors C1 and C2, removing
resistors R9 and R10, and installing 0 ? resistors at
locations R5 and R6.
Tx DAC Outputs
By default, on-board ultra-low-distortion op amps (U4
and U5) buffer the DAC outputs on the MAX19700 EV
kit. The op amps convert the differential signal from the
MAX19700 to a single-ended 50 ? signal. Measure the
buffered output signals at J8 (Q channel) and J9
(I channel).
Measure the differential output of the MAX19700 at the
IDN/IDP and QDN/QDP pads. Full-scale output, offset
voltage, and common-mode voltage functions are con-
trolled through the MAX19700 EV kit software.
8
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